This disclosure relates to integrated circuit devices, and more specifically, to a method and structure to create advanced silicon (Si) and silicon germanium (SiGe) FinFET structures in semiconductor devices.
As the dimensions of modern integrated circuitry in semiconductor chips continues to shrink, conventional lithography is increasingly challenged to make smaller and smaller structures. With the reduced size of the integrated circuit, packaging the chips more closely together becomes important as well. By placing chips closer to each other, the performance of the overall computer system is improved.
FinFET (Fin Field Effect Transistor) has become a preferred CMOS technology at 22 nm. The semiconductor industry has found an alternative approach to planar FETs with FinFETs to reduce leakage current in semiconductor devices. In a FinFET, an active region including the drain, the channel region and the source protrudes up in a “fin” from the surface of the semiconductor substrate upon which the FinFET is located. Due to the many superior attributes, especially in the areas of device performance, off-state leakage and foot print, FinFETs are replacing planar FETs. CMOS FinFET devices have both FinFETs which use n-channels (nFETs) and FinFETs which use p-channels (pFETs).
Strain engineering is highly desired for boosting CMOS performance in FinFET technologies. To boost performance, tensile strain is beneficial for nFET devices and compressive strain is beneficial for pFET devices. Strained compressive high germanium percentage SiGe materials and strained tensile silicon material grown on strain relaxation buffer (SRB) substrates have been touted as a device option for small geometries. However, when SiGe or Si fins are cut into desired lengths, the desired strain relaxes at the fin ends. The loss of strain at SiGe or Si fin ends causes device degradation and variations in device performance.
Therefore, there is a need to fabricate SiGe and Si fins without the fin ends strain relaxation issue.